The present disclosure relates to integrated circuit (IC) packaging, and more specifically, to a three dimensional (3D) IC package with an interposer including a redistribution layer between a top and bottom IC die, and a related method of forming same.
Integrated circuits (IC) are formed in semiconductor wafers during front end of line (FEOL) processing in a semiconductor fab, i.e., up to a first metallization layer over the IC devices. Back end of line (BEOL) processing is any processing performed on the semiconductor wafer in the course of device manufacturing following first metallization, e.g., to enlarge the wiring for interconnection to other devices.
3D IC packages typically are formed by electrically coupling a front side of an IC top die to a back side of an IC bottom die with some interconnections therebetween. Wiring layers on the back side of a bottom die/wafer, which are connected to through semiconductor via (TSV) connections through that bottom die, are limited to wires with line-space dimensions of about 8 to 10 micrometers. The limitation is based on lithography processing capability while the thin bottom wafer is mounted face down on a temporary handler wafer, as part of the three dimensional through semiconductor via (3D/TSV) interconnect processing. Warpage of the thin wafer on the temporary handler wafer prevents high resolution lithography imaging. In addition, the pitch of the TSV connections through the bottom die/wafer to the back side wiring are limited in placement by the minimum line-space dimensions of this wiring layer. In many cases, the pitch requirements of the micropillar interconnects on the front side of a top die to which the TSV interconnects of the bottom die must couple, e.g., of about 30 to 40 micrometers, drive the TSV placement pitch of the bottom die. Larger pitch TSV placements consume larger amounts of area that cannot be used for other circuitry, which is undesirable due to the high cost of advanced node logic wafers. The current line-space limitation of 8 to 10 micrometers for the backside wiring layer of the bottom die only allows partial shrinkage of the TSV footprint. In order to fully reduce the impact of the TSV footprint, a line-space of 1 micron or less is desired.
One approach to create smaller wire dimensions for the bottom die during back side wiring processing is to re-introduce the wafer with the carrier wafer thereon into the fab in which the ICs were made, and then form additional, smaller wiring layers. However, this approach is logistically challenging because current IC fabrication tools are not configured to handle temporary carrier wafers, and those tools typically reside in clean areas with higher levels of particle and other contamination restrictions. Another challenge with mating IC dies is the desire to create a larger number of interconnections between the dies. It is possible to create larger numbers of TSVs connecting to the back side of the bottom die in a small area to increase the number of connections, but there is currently no way to enlarge (fan out) the TSVs to mate with current micropillar spacing on the top die. Another challenge with current 3D IC packaging is that the interconnects of the two dies must be mated in aligned or overlapped fashion.